High performance interconnect architecture for field programmable gate arrays

ABSTRACT

This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.

FIELD PROGRAMMABLE GATE ARRAYS FIELD OF THE INVENTION

[0001] This invention relates generally to Field Programmable GateArrays (“FPGAs”) and, more particularly, to a high performanceinterconnect architecture for FPGAs.

BACKGROUND OF THE INVENTION

[0002] Field Programmable Gate Arrays (“FPGAs”) are popular devices forimplementing electronic circuits. A basic FPGA contains ConfigurableLogic Blocks (“CLBs”), routing matrices and input/output (“I/O”) blocks.The combination of these provides flexibility and enables theconfiguration of almost any digital electronic circuit. The desiredcircuit can be implemented by configuring the CLBs using a softwaretool.

[0003] The interconnect architecture plays an important role infacilitating the configuration of the FPGAs. The interconnectarchitecture is required to provide maximum utilization of the logicresources available on chip, minimize latency, be simple to configureand occupy the smallest possible area on the chip.

[0004] Tiled interconnect architectures are popular because of theirsimplicity and reusability.

[0005]FIG. 1 shows the schematic diagram of a basic “quad line” tile 100used to construct the interconnect architecture. The basic cell consistof configurable logic blocks 101, a band of routing segments 102 andvias 103, 104. The band of routing segments 102 comprises a plurality ofinterconnect segments, each of which connects two CLBs through via 103.The band of routing segments propagates through bent section 105 andthrough cross over layer 106 for connecting the first and the lastinterconnect segments through via 104.

[0006]FIG. 2 shows an interconnect architecture constructed byreplicating the basic cell of FIG. 1. The interconnect segment startsand ends at an interface 201. As shown, for a “quad line” architecture,an interconnect segment traverses four tiles before terminating atanother interface matrix 201. The line segment has bent sections 202 inthe first three tiles and another fragment 203 in the fourth tile wherethe segment terminates. While fabricating a segment, the bent sections202 are placed on a metal layer different from the metal layers forfragments 203. Vias link the fragments 203 and interconnect segments204.

[0007] A similar type of interconnect architecture is described in U.S.Pat. No. 6,204,690. This patent uses a combination of single-lengthinterconnect lines connecting to adjacent tiles, and intermediate-lengthinterconnect lines connecting to tiles separated further apart. Thisarrangement results in an interconnect hierarchy that allows any logicblock to be connected to any other logic block. This also allows forfast paths to both adjacent tiles and tiles some distance away. Longerinterconnect lines may be included as a third level of hierarchy topermit interconnection of widely separated tiles.

[0008] U.S. Pat. No. 5,760,604, provides an interconnect architecturethat uses logic-unit output lines, of more than one length and providesextension lines to increase the reach of a logic unit output line.

[0009] All the patents mentioned above describe symmetric tilearchitectures for a programmable device requiring a physical staggeringof routing lines. A line/group of lines are staggered in a tile tomaintain tile symmetry. These tiles when replicated and placed next toeach other, generate a routing channel with multiple length lines in thechannel.

[0010] The interconnect architecture as described in above referredpatents and any channel generation by tile replication in the mannerdescribed suffers following drawbacks.

[0011] A signal propagating between two ports has to pass through aseries of vias and interconnect layers resulting in increased signaldelays.

[0012] Interconnect layers are extensively bent along the signal pathleading to electro-migration issues.

[0013] Introduction of extra interconnect layers in the physical layoutrestricts other connectivity.

SUMMARY OF THE INVENTION

[0014] To address the above-discussed deficiencies of the prior art, aprimary object of this invention is to overcome above drawbacks andprovide a programmable gate array with good interconnect flexibility.

[0015] Another object of the invention to provide an interconnectstructure that occupies minimum area.

[0016] Yet another object of the invention is to minimize signal latencyby providing straight line interconnect segments.

[0017] It is also an object of the invention to minimize electromigration in interconnect lines.

[0018] To achieve these and other objectives, the invention provides ahigh performance interconnect architecture providing reduced delay,minimized electro-migration and reduced area in FPGAs comprising aplurality of tiles consisting of interconnected logic blocks, that areseparated by intervening logic blocks. Each set of interconnected logicblocks is linked by an interconnect segment that is routed in a straightline throughout and an interconnect layer over intervening logic blocksand is selectively connected to the logic block at each end through aconnecting segment.

[0019] Before undertaking the DETAILED DESCRIPTION OF THE INVENTIONbelow, it may be advantageous to set forth definitions of certain wordsand phrases used throughout this patent document: the terms “include”and “comprise,” as well as derivatives thereof, mean inclusion withoutlimitation; the term “or,” is inclusive, meaning and/or; the phrases“associated with” and “associated therewith,” as well as derivativesthereof, may mean to include, be included within, interconnect with,contain, be contained within, connect to or with, couple to or with, becommunicable with, cooperate with, interleave, juxtapose, be proximateto, be bound to or with, have, have a property of, or the like; and theterms “circuit” and “circuitry” may be used interchangeably and mean anydevice or part thereof that controls at least one operation, such adevice may be implemented in hardware, firmware or software, or somecombination of at least two of the same. Definitions for certain wordsand phrases are provided throughout this patent document, those ofordinary skill in the art should understand that in many, if not mostinstances, such definitions apply to prior, as well as future uses ofsuch defined words and phrases.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The invention will now be described with the reference to theaccompanying drawings, in which like reference numerals represent likeparts, and in which:

[0021]FIG. 1 shows the schematic diagram of the basic cell of aconventional quad line routing architecture.

[0022]FIG. 2 shows the schematic diagram of a conventional quad linerouting architecture.

[0023]FIG. 3 shows the schematic diagram of a conventional fieldprogrammable gate array (FPGA).

[0024]FIG. 4 shows the schematic diagram of an improved routingarchitecture in accordance with the present invention.

[0025]FIG. 5 shows a detailed structure of a tile in the improvedinterconnect architecture.

DETAILED DESCRIPTION OF THE INVENTION

[0026]FIGS. 3-5, discussed below, and the various embodiments used todescribe the principles of the present invention in this patent documentare by way of illustration only and should not be construed in any tolimit the scope of the invention. Those skilled in the art willunderstand that the principles of the present invention may beimplemented in any suitably arranged FPGA.

[0027]FIG. 3 shows the schematic diagram of an FPGA consisting of anarray of spatially distributed programmable logic elements. Theprogrammable logic elements [301] can be connected by programmablerouting elements 303 extending between them. During device operation,these programmable elements operate concurrently in order to performsome intended functionality. The flexibility provided by theprogrammable routing elements and connectors [303 and 302] is animportant factor that determines the routability between theprogrammable logic elements [301]. The routing channel [303] runningorthogonally across the array consists of a number of routing segmentsarranged in a manner so as to offer maximum interconnect flexibility. Anoffset is introduced between the segments in order to achieve goodinterconnect distribution in the channel. FIGS. 1 and 2 delineate such ascheme.

[0028]FIG. 4 illustrates an overview of a preferred embodiment ofchannel construction according to the instant invention. The arrangementinvolves segments spanning four blocks, where a block is the regionencompassed by [403]. The routing tracks [401] have start and finishports at interface matrices [402]. It is clear from the illustrationthat the routing tracks [401] are neither bending at any point in thechannel and nor are they changing any interconnect layers during theircourse of propagation.

[0029] In this type of interconnect architecture, the interconnectdelays are substantially reduced as each routing segment now traversesthe shortest distance between the interface matrix ports. The lineimpedance also goes down because of no intermediate layer change whilethe absence of bends or sharp edges in the track layer eliminates theproblems associated with electro-migration. Finally, area blockage dueto layer change is mitigated as segment sections consist of a singleinterconnect layer.

[0030]FIG. 5 shows a detailed construction view of the routing channelshown in FIG. 4. The interface matrix port layer [501] is seen extendingacross the channel segments. Vias [502] and [503] connect routingsegments [401] to the interface matrix ports [501]. In order to emulatesegment staggering, vias [502] and [503] are shifted at adjacentinterface matrix blocks. The via shifting pattern is cyclic in natureand is seen repeated every four blocks in the present embodiment. Aswill be appreciated by those skilled in the art, the interface portlayer patch [501] simplifies physical layout design and the problem ofstaggering is eventually reduced to a via placement exercise.

[0031] Thus, the routing segment construction methodology in the presentinvention offers superior overall performance over its previouscounterparts without any compromise in flexibility. It is intended thatthe present invention encompass such changes and modifications as fallwithin the scope of the appended claims.

What is claimed is:
 1. A high performance interconnect architecture forField Programmable Gate Arrays (FPGAs), providing reduced signal delay,minimized electro-migration and decreased interconnect area, comprisinga plurality of tiles replicated orthogonally across the FPGA, each tileconsisting of: a plurality of logic blocks; each of which can beselectively connected to one or more logic blocks separated from it byintervening logic blocks, a plurality of interconnect segments, each ofwhich connects two or more logic blocks, that are routed in straightlines through an interconnect layer over the intervening logic blocks,and a connecting-segment provided at the periphery within each logicblock for selectively connecting the associated interconnect segmentwith the logic block.
 2. A high performance interconnect architecturefor field programmable gate arrays as claimed in claim 1 wherein theconnecting segments are fabricated on a metallization layer differentfrom the metallization layer used for interconnect segments tofacilitate crossing over intermittent interconnect segments.
 3. A highperformance interconnect architecture for field programmable gate arraysas claimed in claim 1 wherein the connecting-segments are connected tothe interconnect segments through vias.
 4. A method for providing a highperformance interconnect architecture for field programmable gate arrays(FPGAs) providing reduced signal delay, minimized electro-migration anddecreased interconnect area, comprising the steps of: providing aplurality of tiles replicated orthogonally across the FPGA, providing aplurality of logic blocks within each tile, enabling selectiveconnection between a plurality of logic blocks separated from each otherby intervening logic blocks routing interconnect segments betweenconnected logic blocks in straight lines through an interconnect layerover intervening logic blocks, and providing a connecting segment at theperiphery of a logic block for selective connection of the interconnectline to the logic block.
 5. A method as claimed in claim 4 includingfabricating said connecting segments on metallization layers that aredifferent from the metallization layers used for fabricating theinterconnect segments to facilitate crossing over intermittentinterconnecting segments.
 6. A method 4 including linking of theconnecting-segments to the interconnect segments through vias.